august 1997 f ds8936s dual n-channel enhancement mode field effect transistor generaldescription features absolute maximum ratings t a = 25 o c unless other wise noted symbol parameter f ds8936s units v dss drain-source voltage 30 v v gss gate-source voltage 20 v i d drain current - continuous (note 1a) 5 a - pulsed 20 p d power dissipation for dual operation 2 w power dissipation for single operation (note 1a) 1.6 (note 1b) 1 (note 1c) 0.9 t j ,t stg operating and storage temperature range -55 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a ) 78 c/w r q jc thermal resistance, junction-to-case (note 1) 40 c/w FDS8936S rev.c low gate charge . 5.0 a, 30 v. r ds(on ) = 0.040 w @ v gs = 10 v. high density cell design for extremely low r ds(on) . high power and current handling capability in a widely used surface mount package. dual mosfet in surface mount package. sot-23 supersot t m -8 soic-16 so-8 sot-223 supersot t m -6 so-8 n-channel enhancement mode power field effect transistors are produced using fairchild 's proprietary, high cell density, dmos technology. this very high density process is especially tailored to provide superior switching performance and minimize on-state resistance . these devices are particularly suited for low voltage applications such as disk drive motor control, battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. 1 5 7 8 2 3 4 6 ? 1997 fairchild semiconductor corporation
electrical characteristics ( t a = 25 o c unless otherwise noted ) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 30 v d bv dss / d t j breakdown voltage temp. coefficient i d = 250 a , referenced to 25 o c 29 mv / o c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v 1 a t j = 5 5c 10 a i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v -100 na on characteristics (note 2 ) d v gs(th) / d t j gate threshold voltage temp. coefficient i d = 250 a , referenced to 25 o c -5.4 mv / o c v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 1 2.4 3 v t j =12 5c 0.8 1.55 4 r ds(on) static drain-source on-resistance v gs = 10 v, i d = 5 a 0.033 0.04 w t j =12 5c 0.049 0.064 i d(on) on-state drain current v gs = 10 v, v ds = 5 v 20 a g fs forward transconductance v ds = 5 v, i d = 5 a 8.5 s dynamic ch aracteristics c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1.0 mhz 500 pf c oss output capacitance 350 pf c rss reverse transfer capacitance 120 pf switching ch aracteristics (note 2) t d(on ) turn - on delay time v ds = 10 v, i d = 1 a 7 14 ns t r turn - on rise time v gs = 10 v , r gen = 6 w 13 23 t d(off) turn - off delay time 16 28 t f turn - off fall time 8 16 q g total gate charge v ds = 10 v, i d = 5 a, 14.6 20 nc q gs gate-source charge v gs = 10 v 3 q gd gate-drain charge 4.5 drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current 1.3 a v sd drain-source diode forward voltage v gs = 0 v, i s = 1.3 a (note 2 ) 0.75 1.2 v notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. FDS8936S rev.c c. 135 o c/w on a 0.003 in 2 pad of 2oz copper. b . 125 o c/w on a 0.02 in 2 pad of 2oz copper. a . 78 o c/w on a 0.5 in 2 pad of 2oz copper.
FDS8936S rev.c 0 1 2 3 4 5 0 5 10 15 20 25 v , drain-source voltage (v) i , drain-source current (a) v =10v gs 5.5 5.0 4.5 4.0 3.5 ds d 6.0 7.0 0 5 10 15 20 25 0.5 1 1.5 2 2.5 3 i , drain current (a) drain-source on-resistance v = 4.0v gs 7.0 6.0 5.0 4.5 d 5.5 10 r ds(on ) , normalized typical electrical characteristics figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v =10 v gs i = 5.0 a d r , normalized ds(on) figure 3. on-resistance variation with temperature . 1 2 3 4 5 6 0 5 10 15 20 v , gate to source voltage (v) i , drain current (a) 25c 125c v = 10v ds gs d t = -55c a figure 5 . transfer characteristics. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0.0001 0.001 0.01 0.1 1 10 20 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c a 25c -55c v = 0v gs sd s figure 6 . body diode forward voltage varia tion with source current and temperature. 2 4 6 8 10 0 0.1 0.2 0.3 0.4 v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) t = 125c a t = 25c a i = 5.0a d figure 4 . on resistance variation with gate-to -source voltage.
FDS8936S rev.c 0 5 10 15 20 25 0 5 10 15 q , gate charge (nc) v , gate-source voltage (v) g gs i = 5.0a d 10v 20v v = 5v ds 0.1 0.2 0.5 1 2 5 10 20 30 50 0.01 0.1 0.5 1 5 10 20 50 v , drai n-source voltage (v) i , drain current (a) ds d dc 1s 10ms 100ms 10s 1ms rds(on) limit v = 10v single pulse r =see note1c t = 25c gs a q ja 100us 0.01 0.1 0.5 1 10 50 100 300 0 5 10 15 20 25 30 single pulse time (sec) power (w) single pulse r =see note 1c t = 25c q ja a figure 10. single pulse maximum power dissipation . 0.1 0.5 1 2 5 10 30 50 100 200 500 1000 1500 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area . typical electrical and thermal characteristics 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1c q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 figure 11 . transient thermal response curve . note: thermal characterization performed using the conditions described in n ote 1c. transient thermal response will change depending on the circuit board design.
soic(8lds) packaging configuration: figure 1.0 components leader tape 1680mm minimum or 210 empty pockets trailer tape 640mm minimum or 80 empty pockets soic(8lds) tape leader and trailer configuration: figure 2.0 cover tape carrier tape note/comments packaging option soic (8lds) packaging information standard (no flow code) l86z f011 packaging type reel size tnr 13" dia rail/tube - tnr 13" dia qty per reel/tube/bag 2,500 95 4,000 box dimension (mm) 343x64x343 530x130x83 343x64x343 max qty per box 5,000 30,000 8,000 d84z tnr 7" dia 500 184x187x47 1,000 weight per unit (gm) 0.0774 0.0774 0.0774 0.0774 weight per reel (kg) 0.6060 - 0.9696 0.1182 f63tn label esd label 343mm x 342mm x 64mm standard intermediate box esd label f63tnr label sample f63tnlabel lot: cbvk741b019 fsid: fds9953a d/c1: d9842 qty1: spec rev: spec: qty: 2500 d/c2: qty2: cpn: n/f: f (f63tnr)3 f 852 nds 9959 soic-8 unit orientation f 852 nds 9959 pin 1 static dissipative embossed carrier tape
? 1998 fairchild semiconductor corporation dimensions are in millimeter pkg type a0 b0 w d0 d1 e1 e2 f p1 p0 k0 t wc tc soic (8lds) (12mm) 6.50 +/-0.10 5.30 +/-0.10 12.0 +/-0.3 1.55 +/-0.05 1.60 +/-0.10 1.75 +/-0.10 10.25 min 5.50 +/-0.05 8.0 +/-0.1 4.0 +/-0.1 2.1 +/-0.10 0.450 +/- 0.150 9.2 +/-0.3 0.06 +/-0.02 p1 a0 d1 p0 f w e1 d0 e2 b0 tc wc k0 t dimensions are in inches and millimeters tape size reel option dim a dim b dim c dim d dim n dim w1 dim w2 dim w3 (lsl-usl) 12mm 7" dia 7.00 177.8 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 0.606 11.9 15.4 12mm 13" dia 13.00 330 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 7.00 178 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 0.606 11.9 15.4 see detail aa dim a max 13" diameter option 7" diameter option dim a max see detail aa w3 w2 max measured at hub w1 measured at hub dim n dim d min dim c b min detail aa notes: a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). 20 deg maximum component rotation 0.5mm maximum 0.5mm maximum sketch c (top view) component lateral movement typical component cavity center line 20 deg maximum typical component center line b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation user direction of feed soic(8lds) embossed carrier tape configuration: figure 3.0 soic(8lds) reel configuration: figure 4.0 so-8 tape and reel data and package dimensions, continued july 1999, rev. b
soic-8 (fs pkg code s1) 1 : 1 scale 1:1 on letter size paper di me n si o n s s h ow n be l ow a re in : inches [millimeters] part weight per unit (gram): 0.0774 so-8 tape and reel data and package dimensions, continued september 1998, rev. a 9
trademarks acex? coolfet? crossvolt? e 2 cmos tm fact? fact quiet series? fast ? fastr? gto? hisec? the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. tinylogic? uhc? vcx? isoplanar? microwire? pop? powertrench? qfet? qs? quiet series? supersot?-3 supersot?-6 supersot?-8
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